Semiconductor memory devices may be implemented in a variety of ways. One such implementation is a dynamic random access memory (DRAM). DRAMs may be controlled by a memory controller. The memory controller may regulate access to the DRAMs through commands sent to the DRAMs. For example, the memory controller may issue an activate command to activate a row of a memory array. After a delay of a particular time period, the memory controller may issue a read command to access a column of the activated row. This delay is called the row address to column address delay, or tRCD.
The memory controller may issue such a read command with a precharge command. Although the commands may be issued simultaneously, there must be a delay between the issuance of the read command to the issuance of the precharge command. This delay is called the read to precharge delay, or tRTP. After a column access strobe (CAS) latency delay, or tCL, and a posting time delay, read data becomes available to be read outside the DRAM. Similar time periods and delays apply when a write command is issued.
Another time period, the row access strobe, or tRAS, designates the minimum time after an activate command that a precharge command may be issued. In general, the precharge command is issued after both the posting of the data described above and after the time tRAS after the activate command.
To ensure that the DRAM does not precharge too early, the DRAM has timers to time tRCD, tRTP, the posting time, and tRAS. The DRAM must compare the sum of tRCD, tRCP, and the posting time to tRAS to make sure that the tRAS restriction is not violated if the sum is less than tRAS.
Thus, a DRAM generally has at least two timers and logic to perform a comparison on the values stored in the timers before issuing a precharge command.